TSMC and Intel Showcase Sub-2nm CMOS Technologies at 2026 VLSI Symposium

The 2026 IEEE Symposium on VLSI Technology and Circuits (VLSI 2026) is taking place in Honolulu, Hawaii, from June 14 to 18. The conference has highlighted groundbreaking advances in sub-2nm CMOS logic technologies from industry leaders TSMC and Intel, both targeting mass production by 2027.

Intel introduced its high-performance 18A-P node, an enhanced version of its previously announced Intel 18A platform. The new node achieves 18% lower power at the same frequency and 9% higher frequency at the same power compared to its predecessor. Key improvements include new low-power and high-performance FETs, additional threshold voltages, reduced interconnect resistance, enhanced thermal conductivity, and tighter operating skew. The 18A-P retains Intel's RibbonFET nanosheet technology and PowerVia backside power delivery.

TSMC presented its A16 technology, a 16A-class CMOS logic platform. Compared to the company's N2P 2nm node, A16 delivers 8% to 10% higher speed at the same power and 15% to 20% lower power at the same speed, along with an 8% to 10% increase in FET density. The technology employs an improved nanosheet FET and backside power delivery network, with mass production scheduled to begin in the fourth quarter of 2026.

Beyond near-term nodes, the symposium also featured significant progress on complementary FET (CFET) technology for future generations. Intel demonstrated a monolithic CFET with a 45nm gate pitch on Si(110) substrates and a hybrid stacked CFET combining nFETs on Si(100) and pFETs on Si(110). IBM Research developed a SiGe nanosheet pFET capable of withstanding over 900°C processing for sequential CFET integration. Samsung Electronics showcased a 3D stacked CFET with a 42nm gate pitch and three-layer nanosheet channels, achieving high performance through optimized germanium composition.

The Technology track received a record 469 submissions, up from 349 in 2025 and 355 in 2024. Of these, 99 papers were accepted, resulting in a historically low acceptance rate of 21%. China led in submissions with 161 papers, followed by South Korea (101), the United States (74), Taiwan (50), Europe (34), and Japan (24). In terms of accepted papers, South Korea topped with 23, followed by the US (22), and China and Japan tied at 14 each. The most submitted technology areas were device physics and characterization (109 papers) and memory (107 papers).